The hybrid hiding encryption algorithm, as its name implies, embracesconcepts from both steganography and cryptography. In this exertion, animproved micro-architecture Field Programmable Gate Array (FPGA) implementationof this algorithm is presented. This design overcomes the observed limitationsof a previously-designed micro-architecture. These observed limitations are: noexploitation of the possibility of parallel bit replacement, and the fact thatthe input plaintext was encrypted serially, which caused a dependency betweenthe throughput and the nature of the used secret key. This dependency can beviewed by some as vulnerability in the security of the implementedmicro-architecture. The proposed modified micro-architecture is constructedusing five basic modules. These modules are; the message cache, the messagealignment module, the key cache, the comparator, and at last the encryptionmodule. In this work, we provide comprehensive simulation and implementationresults. These are: the timing diagrams, the post-implementation timing androuting reports, and finally the floor plan. Moreover, a detailed comparisonwith other FPGA implementations is made available and discussed.
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